Counter



Sept. 28, 1954 G. v. NoLDE ETAL COUNTER 5 Sheets-Sheet l Filed April s, 1951 Sept. 28, 1954 G. v. NOLDE ETAL COUNTER 3 Sheets-Sheet 2 Filed April s, 1951 INVENroRs eorge L/ IVe/de BY h'a/ K. 51.* Cla/r Sept. 28, 1954 G. v. NOLDE ET Al.

COUNTER 5 Sheets-Sheet 3 Filed April 3, 1951 INVENTORS George L//Va/de `/z/ K. Si 7a/r Patented Sept. 28, 1954 COUNTER George V. Nolde and Hal K. St. Clair, Berkeley, Calif., assignors to Marchant Calculators, Inc., a corporation ci California Application April 3, 1951, Serial No. 219,060

1.0 Claims. (Cl. 23S-92) The present invention relates to electronic decade counting circuits, and more particularly concerns a counting circuit capable of actuating a plural order memory.

Decade counters have been developed which use cascaded stages ofv vacuum tube trigger circuits as counting elements, for example, the counter disclosed by H. Liishutz in Physical Review, vol. 57, 1940, New Vacuum Tube yScaling Circuits, page 243 et seq. Lifshutz disclosed a four stage counter which is advanced in a straight binary progression by input pulses, i. e., the respective stages represent the numeral values `1, 2, l and 8. The circuit is coded to a cyclic count of ten by an interstage coupling arrangement which interrupts t the binary progression in response to the tenth count and returns the four stages to Zero condi tion.

A somewhat dilerent type of four stage decade counter is exemplified by Grosdof Patent No. 2,521,788, issued September 12, 1950. The Grosdofl counter includes four trigger circuit stages which are cascaded to a non-binary count, the respective stages representing the numeral values l, 2, 2 and 4, or 1, 2, 4 and 2. Grosdoff provides a feedback arrangement for establishing a ten count cycle by resetting the trigger circuit stages before the occurrence of a tenth input pulse.

The present invention is of the general type disclosed by the Liishutz article, supra. The speed and simplicity of such counting circuits, as Well as their reliability or" operation, render them useful as basic counting units in calculating machines. However, a practical calculating machine must have a plural order accumulator, or memory, and since most of the prior art electronic machines have met this requirement by furnishing one decade counter for each memory order, the use of an undesirably large quantity of electronic equipment has been thereby necessitated. This increases the size and initial cost of the entire machine, as well as its complexity and cost of maintenance.

The decade counter of the present invention is adapted to actuate a plurality of memory orders. This is accomplished by sequentially connecting the counter to two or more memory orders through a commutator, and by storing the count in each order in signal retention devices'which have the 4property of retaining their count-indicating condition after they are disconnected from the counter. In the preferred embodiment of the present counter, the signal retention devices are storage capacitors, one such capacitor 2 being coupled to each counting stage at a point, the potential of which rises and falls in accordance with the value-indicating or Zeroindicating condition of the given stage. Four such stages are connected in cascade for operating in binary progression, and means are provided for coding the four binaryv stages to a cyclic count of ten, with a transfer stage for generating and storing an output signal in response to the end of a cyclic count. Another fea-ture of the present circuit is the provision of means'for preventing erroneous interstage coupling during connection of the counter to an ordinal group of storage devices.

It is therefore a primary object of the invention to provide a decade counter which is capable of sequentially actuating a plurality of memory orders. Y

It is another object of the present invention to set a counting circuit directly to a condition indicative of the stored count of a memory order in response to connection of the counting circuit to the said memory order.

It is a further object of the invention to selectively delay the output of a tens transfer signal in a decade counter.

It is another object of the invention to store information representing ordinally accumulated numeral values in a series of small, inexpensive devices.

It is a further object of the invention to restore a counter to a Zero condition subsequent to the dissociation of the counter from one memory order and prior to the association of the counter with a next memory order.

It is another object oi the invention to provide an improved decade counter which is both simple and reliable.

Other objects will appear in the following description of a preferred form of the invention and an alternate embodiment thereof, reference being made to the accompanying drawings in which:

Fig. l is a wiring diagram of the counting circuit showing the capacitor memory and the preferred embodiment of the transfer stage.

Fig. 2 is a table of the charge-bearing condition of the four memory capacitors of a single memory order at the completion of each integer of a countirorn one through ten.

Fig. 3 is a Wiring diagram of an alternate embodiment of the transfer stage.

Fig. l is a Wiring diagram of the counting circuit, showing the discharge tube memory.

GENERAL DESCRIPTION The present counting circuit comprises a pulse .anode potential. `tial of the second triode :is coupled to the grid current of the latter.

input terminal to the first of four vacuum tube trigger circuit stages, which stages are cascaded to count in ordinary binary progression, a gate circuit which is opened in response to the count of an eighth pulse, and a clearing tube controlled by the opened gate circuit and responsive to the count of a tenth input pulse for resetting the countinggstages .to-Zero conditionand for closing the gate-circuit. The-counting circuit further comprises a transfer stage which is set to a transfer-indicatingcondition in response to the count of a tenth pulse, a means for resetting the transfer stage to zero condition at such time as a transfer pulse is required, and meansfor` causing the transfer stage to generate a transfer pulse in response to such resetting. A commutator is provided for sequentiallyassociating Vtheicounterf with a lplurality of memory orders, and means are provided which are responsive to the association of the counter with any given memory order for conf .ditioning the counter zinzaccordance withthe vprevious'ly. stored value lin that order.

".'The Apresent .invention isftherefore based on the principle of actuating twoormore memory orders `bymeans .of a singlezdecadecounting circuit.

The basiccircuit utilized in .thecounting stages .of the invention .is thev well known trigger .circuit of thegeneral type :described in Theory `and Application of Vacuum Tubes .by -I-Ierberty J. Reich. In one of yitssimplest forms, the trigger circuit :includes-two vacuum triodes in which the grid fof thenrst `triode is. coupled to `the anode oiA the second .triode through .a network comprisfinga coupling resistoranda coupling capacitor connected vinfparallel. '.Thefgrid of the second ltriode :is coupled'tothe anode of. .thexiirst triode through a like coupling network. The cathodes @of .both.triodeszareumaintained at a potential which is negative `relative l.toxthe anodes, either :directly vor through suitable wcathode. resistors. LGrid andr anode potentials are .applied to the respective electrodes through separate resistors. It-will appear that such av circuit has two stable `operating conditions, viz., 'with either-.of the two triodes conducting and its companion .triodenonconducting. `This is apparent in that the low plate voltage of .the conducting trioderis impressed .on the grid of .the other triodeand maintains .the

latter biased below conduction.

In operation, .assuming the: 'rst triode l.to be the initially conducting tube, Vifza negative ypulse triodes, the anode current of l.the .first triodeis reduced and its anode npotential ybecomes more positive. Due `tothe connection through the aforesaid coupling resistor, the grid potential of the second triode is raised, biasing the second triode to conduction and thereby lowering' its The decrease in .anode potenof .the iirsttriode, further c reducing the anode vThis action continues until the anode current of the first triode is cut oir. The second .triode then remains conducting until ytheapplication of another negativepulse to the A grids of the two ftubes,when the .tube operating :conditions ,are again reversed.

Counter Referring to Fig. `1, each .of fourcounting `stages comprises a respective.triggercircuit H,

I2, I3,anol'l.4. vEach trigger circuit includes a duotriode such as l5, having a left-hand section It and a ri'ghthandsection I1. The right-hand `lsection hereinafter designated as the "normaP Idition.

-Anodepotential is supplied to the abnormal section of each stage from a positive terminal i-B of a source of unidirectional potential ,through an anode resistor 2i), and to each normal section through two series anode resistors El and The combined value of resistors 2| and 22 `is substantiaillyY equal to the value of resistor 20. rThe common cathode of each trigger tube is connected .by;a .cathode return lead 23, common to all stages, and a lead 2t, to a negative terminal `B -off-a source of unidirectional potential, cornpleting the anode-cathode circuit of each section. Thenormal grid of each` tube is coupled to the ,abnormal anode through a resistor 25 paralleled by a capacitor El, and the abnormal grid is coupled to the normal anode by a resistor 28 lparalleled by a capacitor 3Q. Each lnormal grid is connected -to a point 3i on a respective poten- .tialdivider comprising terminal +B, abnormal anode resistor 2D, coupling resistor 25, a resistor 32,*a grid return lead 33, common to all stages,

.the anode circuit of a normally conducting pentode clearing tube 34, a cathode return lead 35, vand a negative terminal Bi of a source of unidirectional potential. The function of the clearingltube will ybe described in detail hereinafter. rIhe grid of each abnormal section is connected ltoa pointv 3l on a respective potential divider comprising terminal -l-B, normal anode resistors 2i and 22, coupling 28, a resistor 33, a grid return lead til, common to all stages, a lead 4 l, a resistor 42, cathode return lead 35, and terminal BL The value-of resistor @2 is chosen as substantially equal to the conducting .plate resistance or pen* tode 3ft-to .maintain the two grid leads 33 and lil at approximately the same potential above El. A by-,pass capacitor t3 is connected between lead 4l and lead2frto'shunt fluctuations in the potential of grid return lead lli) to terminal -B. Summarizing, the grid of each sectionof a trigger circuit tube is maintained at a potential between ,-lfand .Bl by tapping the grid to a vpoint on a respective potential dividing network. Each of the normal grid potential dividers includes the clearing tube 3d, and each of the abnormal grid potential dividers includes the resistor 32, which is parallel to tube 34. By proper choice of the resistor values of the potential divider networks and the respective potential values of terminals -l-B, -B, and -BL the grids of each stage are .maintained within such a range that each stage acts as a trigger circuit of the type described rhereinbefore.

A pulse input terminal M is symmetrically coupled to both grids of the rst trigger circuit stage through a capacitor 15, which isolates the counting circuit from the pulse generator, and through a. respective coupling capacitor lit and 4'! for isolating each of the two grids from the other. Negative input pulses are impressed on -terminal 134 and are thereby coupled to both grids. The first input pulse cuts off the anode current of the initially conducting normal section of the rst stage to cause the abnormal section to conduct. .Each subsequent input pulse likewise reverses the operating condition of the first stage. A resistor 158 is connected between the grid input of each stage and terminal -B by cathode return lead 23 to drain charges stored by coupling capacitors it and 41 due to the input pulses.

The normal anode of each stage, except the last, is symmetrically coupled to the grid input of each grid of the succeeding stage through a coupling capacitor Sti and a rectifier 6 I. Rectifier 6l is connected in such a direction that it passes negative pulses from each stage to the next succeeding stage, while blocking negative pulses in the reverse direction. A respective resistor 62 between each two successive stages is connected to the cathode return lead 23 from a point between capacitor 5l) and rectifier 6l, and cooperates with capacitor 6i] to differentiate pulses from each stage to the succeeding stage.

On the first count, the potential of the normal anode of the first stage rises due to the decreased anode current through resistors 2| and 22. This rise, differentiated into a positive pulse by capacitor Eil and resistor 62, is blocked by rectifier Eil. On the second count, the normal section of the first stage resumes conduction and the anode potential of the normal plate falls. This potential drop, differentiated into a negative pulse, is passed by rectifier Si and impressed upon both grids of the second stage, reversing conduction in that stage. In the same manner, each of the four counting stages, except the first, is reversed once in response to two reversals of the preceding stage.

Since four binary counting stages, such as described above, would, if unmodified, count to fifteen and return to zero condition on the sixteenth count, it is necessary to provide special means for Zeroizing such a counter if it is to be cleared on any count other than the sixteenth. To achieve the zeroizing on the tenth count, as is required in the present decimal system counter, the above-mentioned electronic gate is provided to be opened on the eighth count, and a clearing tube is provided to be actuated on the tenth count by a pulse passed through the opened gate. Actuation of the clearance tube zeroizes the four counting stages and closes the gate, thereby returning the circuit to initial zero condition.

rIhe normal grid of the fourth stage is connected by a lead E3, a resistor 64 and a lead (i5 to the grid of the right-hand section 6l' of a duotriode t6. Tube S6 is arranged as a gate, the right-hand section El thereof being connected as a normally conducting cathode follower, and the left-hand section B8 being connected as a normally blocked amplifier. Anode potential for section Sii is supplied directly from terminal -l-B, whereas anode potential for section (i3 is supplied through an anode resistor l0. The cathodes of both sections di and 63 are connected to terminal Bi by a common cathode resistor 'Il and cathode return lead 35. The grid of amplifier section 68 is connected to the normal grid of the first counting stage by a coupling capacitor l2 and a lead T3, and is biased to a potential intermediate -B and -BI through a resistor 14, a lead l5, and a potential divider comprising a pair of resistors i5 and 'IS connected between -B and -BL The anode of section 68 is connected by a coupling capacitor 'l1 and a lead 18 to a first grid of the above-mentioned normally conducting pentode clearing tube 34. The first grid of tube 34 is returned to terminal -BI by a resistor 8c, a lead 8i, and cathode return lead 35. The second grid of tube 3d is biased to B potential through lead 24 and a resistor 69. The third grid of tube 34 is connected to the cathode.

The relative potential values of terminals B, -B and -BI are such as to maintain tube 34 normally conducting.

It will be recalled that the anode circuit of the clearing tube 34 forms a part of the respective series voltage divider network to which each normal grid of the counting stages is tapped. It therefore appears that if conduction of the clearing tube is cut off, the current flow is decreased through the respective potential divider associated with each normal grid of the counting stages, consequently the potential of each normal grid rises, causing all four stages to conduct normally, thereby clearing the counter to a zero indicating condition. Operation of the clearing circuit cuts off conduction of the clearing tube in the following manner to perform the above-describedclearance of all stages.

During the time the fourth stage conducts normally, its normal grid potential is high and is impressed on the grid of the cathode follower section (i1 of gate tube '66. This high potential maintains section 61 conducting. The anode current of section 51, flowing through the common cathode resistor 1I, causes a constant potential drop across that resistor, maintaining the cathode potential of amplifier section 68 far enough above -BI potential that the amplier section cannot conduct. Therefore, the gate comprising tube 5S is maintained closed as long as the fourth counting stage conducts normally. A positive clearance test pulse is impressed on the grid of amplifier section 68 each time the rst counting stage reverses from abnormal to normal conduction, i. e., in response to each even-numbered input pulse. This is due to the rise in potential of the rst stage normal grid on the even counts. rihe positive pulse so formed is coupled to the grid of amplifier section 68 through lead 'i3 and capacitor l2. However, these positive pulses are of insufficient magnitude to bias section 68 to conduction as long as the normal conduction of the fourth stage maintains the gate closed as described above.

Since the four counting stages are reversed in accordance with the ordinary binary progression described ,hereinbefora it will appear that the fourth counting stage is reversed to abnormal conduction for the iirst time on the eighth count, lowering the fourth stage normal grid potential due to the increased drop across the fourth stage abnormal anode resistor 20. This decreased potential is impressed on the grid of cathode follower section Ei'l by lead t3, resistor 64, and lead (i5, lowering the grid bias on section 6l to decrease the potential drop across cathode resistor li and thereby lower the cathode potential of amplier section B8 towards Bl level. The drop in cathode potential of section 68 is sufficient to bias that section to a potential which is slightly below conduction level, so that the next positive pulse impressed on its grid is amplified to initiate the clearance operation. It will be recalled that such a clearance test pulse is coupled from the first counting stage to the grid of section 558 in response to each even-numbered input pulse. Therefore, when the gate 66 is opened in response to the eight pulse, in the manner described above, a positive pulse is impressed on the grid of section 68, and if allowed to be amplied by the opened gate circuit, would prematurely initiate clearance, since clearance must occur in response to the tenth, not the eight, pulse. To delay the opening of gate 6B until the recession of the above-mentioned positive pulse on the eighth count, abby-.pass f capacitor 82 r-is i connected .in parallel to the gategcircuit cathode resistor f Tl Therefore, when the cathode followersection El is biased .todecreased-conduction; by a negative pulsexon the eighth count, as described above, its cathode potential'drops exponentially: due to the discharging of capacitor B2 through cathode resistor :1,i. [By :proper'choice of the'values of resistor 'H andycapaciton 82,; the rate of fall in cathode potential .of the-gate; tube is kept surficiently slow to maintain ther amplifier section E biased'w'ell ,below conduction,-and therefore the gate closed, .until approximately the ninth count,;,at.f,which time thepeghth count positive pulseahas disappeared frorrrthe amplifierY section grid.

Inresponse tothetenthinputpulse, i. e., the next even-numbered .pulse'following the-eighth, anotherpositive pulse is fed from the first stage normal grid-to the amplilersection 68, and is there amplied. rIhis pulse'appears onv the -plate ofrsection 68. as anega-tive ,clearance initiating pulse and is coupled ,through capacitor l'l'and lead :18 tothe rst @gridy of the clearing tube 3ft, biasingthe clearing tube below conduction to raise the normal grid potential of each counting stage-,and therebyclearthe counter to zero condition as described. hereinbefore At the; termination ofthe single clearancetest pulse'whioh isfam'pliedby section 68 of the gate tube, the anode potential'of that section rises, returning the nrst grid :of theclearing tube 3A to conduction level. The anode current through tube 3e, andA therefore the current through the potential divider associated with each normal gridpis:therebyrestored to the usual operating levelin [preparation: for further counting.

When thesffourlthstage is reversed to normal conduction in Aresponse tocutoff of 'the clearing tube. the potential of i ther `fourth stage normal grid rises, This'potential rise is impressed on the grid .of the cathode. follower section El of gate tube 56. 'through vlead 63, resistor 54, and lead B5, and biases section 6l to increased conduction. Consequently, thecathode potential of thev gate tube G rises,biasing amplifier section 68 well below conduction to close` the gate. Therefore, at thea end-'ofthe tenth count, the four Counting stages and' thegateand clearing tubes are in initial -zerocondition in preparation for further counting.

Preferred embodiment of memory The present-counting circuit is. adapted to be associated, seriatimgwith a plurality -of memory orders for storing, in each such order, information which'represents .the sum of the respective stored. and selected ordinal values. At the time the countingV circuit Ais-vassociated with a given memory order, the condition of that order, representing'the .total previously stored ordinal value, positively presets thefour counting stages to respective condi-tions of operation which, collectively, yrepresent the said stored ordinal value. Following;such-presetting, a number of pulses, representing the :selected ordinal value which is to be added to the stored value, is `introduced into the counting circuit, advancing the circuit' to a representation'of-the-sum of the vaforesaid selected .and stored values. The condition of the particular memory .order which is connected to the-counter during a given count is progressively alterednunder control of thecounter and, at the termination 4of :the: input. pulses, likewise represents: the, sum of; .theH selected. -and= stored values.

.fiInt theV ypreferred Iembodiment-shown in Fig. 1, each'pmemory order-comprises four memory capacitors Eli-53, -onesuch capacitor being associated with each ofy the four counting stages. One terminal of each memory capacitor is grounded, the other terminal being connected by a lead 33 to the respective associated counting stage at a respective point 8d between the two normal section anode resistors 2l and 22. During normal conduction of any stage, the potential of point Sli is lower thanzduring abnormal conduction of that stage. This .isidue to the anode current through anode resistors 2l and 22 during normal conduction. The potential of each point St is impressed by' lead'83 directly on the associated memory capacitor'll-ES, and, therefore, each rise or .fall of that potential augments or diminishes the charge on the capacitor. Therefore, the respective charges on capacitors .E6-53, taken collectively, represent, in a four signal code, the total stored count following each input pulse.

Fig.' 2 illustrates the charge-bearing condition of Athe iour memory capacitors Eil-53 at the end of each count, i. e., after the four counting stages have reached a stable condition following each input pulse into the counting circuit. 'Each row of the chart in Fig. 2 bears a reference numeral 513-53 and represents the corresponding memory capacitor. Each column bears a number 0-10, representing the total'number of input pulses prior to the indicated condition oi the four capacitors. An X in any position indicates that the designated capacitor is charged to the abovementioned higher potential level upon completion'of the designated count; the absence of an X in any position indicates that the designated capacitor is charged to the lower potential level uponcompletion of the indicated count. It is noted that after the tenth count, all four memory capacitors of the order being considered are charged to the lower potential level, i. e., are collectively inthe zero-indicating condition.

Alternate embodiment of memory Fig. 4 Lillustrates a neon tube memory and the circuitry for associating the same with the four countingl stages. In this embodiment of the circuit, a respective neon tube or similar gas discharge device l' is coupled to each count-ing stage'and is caused to conduct or not conduct in accordance with the abnormal or normal condition of the associated counting stages. Corresponding elements of Figs. l and 4 are assigned the same reference numerals, and only those components of theA circuit of Fig. 4 which differ from the circuit of Fig. 1 will be described. The counting action, interstage couplings, and decimal coding are identical as between the two circuits.

'As-shown in Fig. 4, the abnormal anode resistor of each stage is divided into three unit resistors, HB, Hi and H2, and the normal anode resistor of each stage is a single unit H3. One electrode, hereinafter designated the cathodef of the neon tube associated with each stage is coupled to a'point I lli between the abnormal anode resistors Ht and lil of the associated stage by a circuit comprising a capacitor H5, lead 83 and commutator contacts 35. The abnormal grid of each stage is coupled to a respective point H8 between the associated capacitor H5 and the associated commutator contacts 85 by a respective circuit comprising a capacitor il?, a resistor H8 and a lead H9. The point H6 in each stage is grounded through a respective resistor 20. They-cathode of -each'neon tube H38 is grounded 9. through a respective resistor |2| and a common lead |22. The second terminal, hereinafter designated the anode, of each neon tube |98 is connected by a common lead |23 to the positive terminal +132 of a source of unidirectional potential. The +B2 potential, which is therefore applied across each neon tube, is sufiicient to sustain conduction in each of these tubes, but is insuflicient to initiate such conduction. Opertaion of the memory is as follows.

Assuming that the rst stage neon is not conducting and that the rst stage trigger circuit is conducting normally, an input pulse impressed on input terminal G4 reverses the rst stage to abnormal conduction in the manner described hereinbefore. The increased current through abnormal anode resistors liti, iii and ||2 causes the potential of point H4 to drop, coupling a negative pulse to the cathode cf the first stage neon through capacitor |55, lead 33, and commutator contacts 95. rlhis pulse is conducted to ground through resistor I2! and develops sufficient potential across resistor |2| to lower the cathode potential of tube |93 to ignition level, thereby ring the tube` The -i-BZ potential is sufficient to sustain conduction in tube |08, as mentioned above.

When the first stage trigger circuit is subsequently reversed to normal conduction on the next count, the potential at point ||4 rises and a positive pulse is coupled to the cathode of tube |98 through the circuit described above. This pulse is likewise developed across resistor |2| and raises the cathode potential of tube |08 sufficiently to extinguish that tube.

Count storage in the second, third and fourth stages is accomplished in the identical manner, so that the conduction of a neon in any stage represents, and is concurrent with abnormal conduction of the associated trigger circuit stage.

It will be recalled that each order of the memory must preset the counter to the value stored in the memory order when the counter is associated, by the commutator, with that order. Furthermore, the counter must be zeroized prior to being associated with each memory order. Thus, when the commutator connects the counter to a given memory order, any conducting neon tube or tubes in the given order must cause the assoeiated trigger stage or sta-ges to conduct abnormally, and any non-conducting neon must have no effect upon its associated trigger stage.

If any neon tube |98 is conducting when it is associated, by the commutator, with the counter, its cathode potential is higher than the potential of the point H6 in the corresponding stage, due to the drop across cathode resistor |2l. Therefore, a positive pulse is coupled to the abnormal grid of the trigger circuit through commutator contacts 85, lead H9, resistor IIB and capacitor I I'|. This pulse raises the potential of the abnormal grid of the trigger circuit, thereby reversing the stage to abnormal conduction to represent the count-indicating condition of the associated neon tube.

The above-mentioned positive pulse from the cathtode of tube |98 is also impressed on point I I4 of the associated trigger stage through commutator contacts 85, lead 33, and capacitor II5. In order to prohibit this pulse from affecting the normal grid of the trigger circuit, a respective capacitor |24 is connected between ground and a point |25, in each stage, between anode resistors III and ||2. Capacitor |24 shunts the above-mentioned positive pulse to ground, pre- 10 venting it from being coupled to the normal grid through abnormal anode resistor I I2 and the cross-connected coupling capacitor 2l.

Preferred embodiment of transfer circuit If the sum of any accumulated ordinal value exceeds ten after being augmented by the selected value entered into that order, a transfer count must be entered into the next higher order. Since, in the present invention, a single counting circuit is used to actuate a plurality of memory orders, it is necessary to store the transfer count until the counting circuit is connected to the memory order next higher than the order in which such transfer count was generated.

In the preferred embodiment of the transfer circuit, shown in Figs. l and 4, a transfer stage dll, comprising a trigger circuit, is connected in cascade to the fourth counting stage. The transfer stage is actuated in the same manner as are the counting stages. Pulses are coupled from the normal anode of the fourth counting stage to the transfer stage through a circuit comprising coupling capacitor S0 and a triode Si. The grid and cathode of tube 9| are connected by a resistor 92 so that each negative pulse coupled from the fourth stage and impressed on the cathode of tube 9| causes that tube to conduct. Thus, tube 9| functions normally as a diode, performing the same functions as interstage rectiers 6| described hereinbefore.

It will appear that a negative pulse is coupled from the fourth counting stage to the transfer stage only upon the tenth count, when the fourth counting stage is reversed from abnormal to normal conduction by the clearing tube 34. This pulse reverses the transfer stage from normal to abnormal conduction and constitutes the storage of a transfer count.

At the time when it is desired to make use of the transfer count, a negative transfer test pulse is applied to the abnormal grid of the transfer stage through a test terminal 93 and lead 94. If no transfer count has been stored, this negative pulse merely biases the abnormal stage farther below conduction. However, if a transfer count has been stored, the abnormal section of the transfer stage is conducting and is biased below cutoff by the negative transfer test pulse, thereby reversing the transfer stage back to normal conduction. When the normal section of the transfer stage resumes conduction, its anode potential drops, coupling a negative pulse to a transfer output terminal 91 through a coupling capacitor 95 and a lead 96.

It is to be noted that the potential divider networks for both the normal and the abnormal sections of the transfer stage are completed to -Bl through grid return lead dil, lead 4 I, resistor 42, and cathode return lead 35 so that the transfer stage, unlike the counting stages, cannot be reversed by cutoff of the clearing tube 34.

Commutation Following the entry of a selected ordinal number of pulses into the counting circuit, the counter is disconnected from the four memory capacitors or neon tubes with which it was associated during such entry. The counter is then connected to the group of memory devices constituting a next memory order. A conventional commutator with four contacts may be used to perform this seriatim switching of the counter. The commutator contacts are schematically shown in Fig. 1 at 85, each pair of contacts being interposed between a respective capacitor 51)-53 and its associated lead B3l to a counting stage.

During each commutation interval, the counter is cleared while it is disconnected from all memory orders. `For this purpose, a negative pulse is applied from any conventional source to a clearing terminal 86. Terminal 86 is coupled to the second grid of the clearing tube Mby leads 8'! and 88, and a coupling capacitor 89. The nega-k tive pulse so coupled to tube 34 biases that tube below conduction, whereupon thecounting stages are cleared in the manner fully described hereinbefore. In order to isolate the transfer stage during the inter-order clearance, and thereby to prevent an erroneous transfer storage during such clearance, the negative clearing pulse which is impressed on terminal 8G is also coupled tothe grid of the above-described triode t, by a lead Sl` and a capacitor 93,'biasing tube B l' so far below conduction level that vit will not conduct a negative reversing pulse received from the fourth stage as a result of the clearance.

Upon connectiony of the counting circuit'toany given memory order, the charges Whichhave been stored, during a .previous count, on the respective memory capacitors in that order,` are impressed on the points S35 `of the associated counting stages. Since all. four counting stages have been set to normal conduction immediately prior to this time, asy described above, the abnormal grid of each counting stage is at low potential. When the memory capacitors of the given order-are connected to the counter, those capacitorswhich have ybeen previously charged to the vhigher potential .level impress a risev in potential `on their respective associated abnormal grids through the resi'storsZZ .and 28 ofthe associatedy stages, reversing the affected stages to abnormal kconduction, and thereby presetting thecounter tothe value'previously stored in the memory order. In each stage which is so reversed-'duringvpresetting the increasedpotential drop across the associated abnormal anode resistor 20 forms a negative pulse at the abnormal anode'. However, the interstage rectiers. I, described-hereinbefore, prevent the feedback of any suchnegative pulse to the preceding stage.-

Fig.. 'illustrates an Valternate*embodiment of the transfer stage and shows its connection to the fourthstage of the counter.

When the fourth countingfstageis reversed to normal conduction on the tenthl count, as described hereinbefore, the'potential of itsnormal` plate at point. Hwdrops due tothe increased current through anode resistors 2l and 22.- This voltage drop is coupled through ay coupling capacitor lill and a rectifier IDE to a transfer storage capacitor |63, storing a negative charge thereon; A resistor IEM-is connected to vground from a point between capacitor IM and rectifier i112 yto develop a voltage below ground from the above-.mentioned negative pulse Vreceived from the counter. Capacitor H03 is connected to one contact of a normally open switch m5. The other contact of switchl lisconnected .to a transfer output terminal l @6. When itis desired. to. use the transfersignal, switchltl is closed by any conventional means, such as a cyclic. commutator, and if a transfer charge'has. been` stored on capacitor |03, it is impressed on. the transfer output terminal IMS.: The output voltage is developed-across a resistor I lll shunted between the output terminal and ground.

We claim:

l. In an electronic counting circuit having four trigger circuit stages connected in cascade to provide operation of each of said stages except the first in response to two operations of the'next preceding stage, and having means coupled to the rst of said stages for applying input pulses thereto, each of said pulses being effective to operate said rst stage; the combination of, output means for deriving a pulse'from the fourth stage in response to ten of said input pulses, said output means including, a normally closed gate circuit coupled to the fourth stage and biased thereby to an open condition in response to an eighth input pulse, a clearing tube normally biased by said gate circuit to an initial mode of operation, means responsive to the occurrence of a tenth input pulse for coupling a pulse from the first Vstage through said gate to bias the clearing tube to a second mode of operation, a coupling from the clearing tube to the fourth stage for operating the fourth stage inresponse to said second condition of operation of the clearing tube, and a coupling from the clearing tube to the second stage and effective in response to said second condition of operation of the clearing tube for preventing aY normal operation of the second stage.`

2. In an electronic counting circuit, the combination of, a plurality of trigger circuit stages each stage including a pair of electron discharge elements having a respective anode, cathodeand grid, the grids and anodes of each pair of said elements being cross-connected, means connectingY said stages in cascade to provide operation of each of said stages except the first in-v response to two operations of the next preceding: stage, means coupled' to the rst of said stages for applying input voltage'pulses thereto, a normally closed gate circuit coupled to a grid -of thelast stage and biased thereby to an .open condition in response to a predetermined count, means for coupling a clearance test/pulse from the first stage to the gate circuit in response to eachy two ofl said input pulses,a normally ineffective clearing tube, means responsive to the coincidence of a clearance test pulse and said open condition of the gate circuit for coupling a clearance initiating pulse from the gate circuit to the clearing tube to biasthe clearing tube to-an effectivecondition of operation, a coupling-from the clearing tube to the last stage for operatingthe last stage inresponse-to said effective condition of the clearing tube, a coupling from the clearing tube to the-second stage and eifective in response to said effective condition of the clearingtube to'prevent anormal operation .of the second stage; and means including-a part of the last stagevresponsive .to the last aforesaidV operation of the last stage for generating an output pulse.

3. In an electronic counting circuit having four trigger circuit stages connected in cascade torprovide operation of each of saidstages in response tor twol operations of the neXt'preceding-"stage, and .having means Icoupled to the first of1.saidy stages for applyingrinput -voltage pulses thereto,A

each of said pulses being eifective to operate said iirst stage, selectively operablewmeansfor clearing said trigger circuits to an original. conditionA thereof, .said means including, a. clearing'.- tube normally biased toan initial conditionfof operation, selectively operable means coupled tothe clearing tube for applyingvavoltagepulse thereto to bias the clearing tube to a second condition of operation, and arespective coupling from. the

clearingtube to each of` said triggercircuitsfor applying. a clearing signal to eachfoffsaid trigger.

circuits in response to said second condition of operation of the clearing tube.

4. A decade counter having, a plurality of counting stages coupled in cascade to render each of said stages except the rst operable in response to two operations of the next preceding stage, means coupled to the counter for applying input voltage pulses thereto, and means inter-coupling certain of said stages for causing the counter to complete a cycle of operation in response to ten input pulses; the combination of, a respective memory device associated with each counting stage, and means for coupling each memory device to its respective associated counting stage for enabling said counting stage to set its associated memory device to a value-representing condition and to reset the same to a zero-representing condition, respectively, in response to alternate operations of said counting stage, a transfer stage comprising a transfer device normally in a first condition of operation, a coupling between said transfer device and the last counting stage for causing the transfer device to assume a second condition of operation in response to the completion of a cycle of operation, selectively operable means effective in coincidence with said second condition of operation of the transfer device for causing the latter to generate a transfer pulse, a normally ineffective transfer blocking device interposed between the last counting stage and the transfer stage, a selectively operable control means coupled to said blocking device for rendering the latter effective to disable said coupling between the fourth counting stage and the transfer device.

5. In a decade counter having, a plurality of counting stages coupled in cascade for operation in binary progression, means intercoupling certain ones of said stages for causing the counter to complete a cycle of operation in response to ten input pulses; the combination of, a respective memory capacitor associated with each counting stage but normally disconnected therefrom, means for connecting each memory capacitor to its respective associated counting stage for enabling each charged capacitor to cause operation of its respective counting stage, means coupled to the counter for applying input pulses thereto, and means including a part of each counting stage for charging and discharging, respectively, each memory capacitor in response to alternate operations of its associated counting stage.

6. In a decade counter having, a plurality of counting stages coupled in cascade for operation in biliary progression, and means inter-coupling certain ones of said stages for causing the counter to complete a cycle of operation in response to ten input pulses; the combination of, a iirst ordinal group of memory capacitors, one of said capacitors being associated with each counting stage but normally disconnected therefrom, means for connecting each of said memory capacitors to its respective associated counting stage to enable each charged capacitor to cause operation of its respective counting stage, means coupled to the counter for applying input pulses thereto, and means including a part of each counting stage for charging and discharging, respectively, each of said memory capacitors in response to alternate operations of its associated counting stage, a second ordinal group of memory capacitors, one of said second group being associated with each counting stage, and means for commutating each counting stage from its first to its second associated memory capacitor.

7. In a decade counter having, a plurality ofcounting stages coupled in cascade for operation in binary progression, and means inter-coupling certain ones of said stages for causing the counter to complete a cycle of operation in response to ten input pulses; the combination of, a respective conducting or extinguished discharge tube associated with each counting stage but normally disconnected therefrom, each of said tubes having at least twoelectrodes, means coupled to the electrodes of each of said tubes for applying thereto a potential which is insuicient to initiate conduction in any of said tubes but which is suicient to sustain conduction in any of said tubes, means for coupling one electrode of each oi said tubes to its associated counting stage for enabling each conducting one of said tubes to cause operation of its respective counting stage, means coupled to the counter for applying input pulses thereto, and means including a part of each counting stage for firing and extinguishing, respectively, the associated discharge tube in response to alternate operations of a counting stage.

8. A decade counter having, a plurality of counting stages coupled in cascade for operation in binary progression, and means intercoupling certain ones of said stages for causing the counter to complete a cycle of operation in response to ten input pulses; the combination of, a first ordinal group of conducting or extinguished discharge tubes, one of said tubes being associated with each counting stage but normally disconnected therefrom, at least two electrodes for each of said tubes, means coupled to the electrodes of each tube for applying thereto a potential which is insufficient to iniate conduction in any of said tubes but which is suincient to sustain conducton in any of said tubes, means for coupling one electrode of each of said tubes to its associated counting stage for enabling each conducting one of said tubes to cause operation of its respective counting stage, means coupled to the counter for applying input pulses thereto, means including a part of each counting stage for ring and extinguishing, respectively, the associated discharge tube in response to alternate operations of a counting stage, a second ordinal group of discharge tubes, a respective one of said second group of tubes being associated with each counting stage, and means for commutating each counting stage from its first to its second associated discharge tube.

9. In a counting circuit having four trigger circuit stages connected in cascade to render each of said stages except the first operable in response to two operations of the next preceding stage, and having means coupled to the iirst of said stages for applying input pulses thereto, each of said pulses being effective to operate said first stage; the combination of, a respective memory device associated with each trigger circuit stage, means coupling each memory device to its associated trigger circuit for enabling said trigger circuit to set its associated memory device to a value-representing condition and to reset the same to a Zero-representing condition, respectively, in response to alternate operations of said trigger circuit, output means for deriving a pulse from the fourth stage in response to ten of said input pulses, said output means including, a normally closed gate circuit coupled to the fourth stage and biased thereby to an open condition in response to an eighth input pulse, a clearing tube normally biased by said gate circuit to an initial mode of operation, means reaecogsoa.;

sponsive tothe occurrence of-:a: tenth input` pulse for coupling a pulsefrom the :first stage through;

said gate to bias the clearing'ftubeito ausecond mode of operation, a couplingffrom thefclearing tube to the fourth stageffor operating thelatter in response to the said second condition of'foperation. of the clearing tube, and a coupling-from the clearing tube to the second stage-andfefective in response to said second condition oftoperationV of the clearing tube for preventing operation of the second stage;`

10. In a decade counter having, apluralityo'f counting` stages coupled in cascade for operationl in binary progression, means interconnecting certain` ones of said stages for causing' the counter to complete a cycle 0I operation in response to ten input pulses; the combination of-,'

a respective memory device associated with each counting stage but normallyfdisconnected therefrom, means for connectingeach memorydevice to its respectivev associated counting stage for enabling each device to cause operation of its respectivescountingestage, -meansfcoupled .to *the counter for applyinginput .pulses thereto, and.

means including apart of each counting. stage for activating; and s deactivatiingi respectively; eachV memoryidevice inxresponseto alternate operations of its :associated countingfstage. v

References,-CitecL-inlthe le of this patent UNITED 'STATES'PATENTS OTHER REFERENCES- 

